Compiled Circuit

Using TopQAD's Compiler and QRE services, you can output a detailed list of the lattice surgeries performed in the memory zone of the core processor. This includes which patches are required for each lattice surgery and the order in which these surgeries are performed. The output file is a JSON file in the format <time step>: [<operation ID>, [<patch connections used by the lattice surgery>]]. The patch connections are described by the patch identifier and edge elements as defined in the Microarchitecture Layout file format page.

In the example shown below, at time step 0 there is a lattice surgery between the Z edge of the 0th patch where magic states are injected and the Z edge of computational qubit 1, using bus tiles 1, 2, and 6.

[
    {"0": [
        [0, [[["m0", "Z"], 1], [1, 2], [2, 6], [6, ["q1", "Z"]]]], 
        [2, [[["m1", "Z"], 4], [4, 7], [7, 5], [5, ["q0", "Z"]]]]]
    ]},
    {"1": [
        [1, [[["m0", "Z"], 1], [1, 2], [2, 6], [6, ["q2", "Z"]]]], 
        [3, [[["m1", "Z"], 4], [4, 7], [7, ["q3", "Z"]]]]]
    ]}
]