Quantum Architecture Basics

Benchmarking utility-scale quantum software is essential for guiding the development of quantum computers, years before standardized software engineering practices are devised for executing such quantum software on these systems. Thus, in this section, we introduce terminology, motivated by that used in classical software engineering, which is necessary in order to detail the power of TopQAD for benchmarking and design.

Instruction Set Architecture

In computing, an instruction set architecture (ISA) details the basic operations and formats that a processor supports, and therefore defines how software is compiled for execution by the processor. In classical computing, the ISA includes, for example, supported instructions, data types, registers, and input/output models [1]. In quantum computers, the ISA may include specifications regarding the logical gate set that will be run on the processor and, since quantum computers are intrinsically prone to errors, how fault-tolerant operations such as long-range teleportation will be executed.

Microarchitecture

A microarchitecture defines how a particular processor will implement an ISA. It details the constituent parts of the processor and their connections [2]. In classical computing, possible constituent parts include modules such as the arithmetic logic unit (ALU), floating point units (FPU), and single instruction, multiple data (SIMD) microarchitecture. However, since quantum computers require quantum error correction (QEC), the microarchitecture of a quantum processing unit (QPU) has logical and physical levels. The possible constituents of a logical microarchitecture are modules, for example, core processors, memory and QROM registers, and magic state factories (MSF); these can be further broken down into logical subcomponents (e.g., logical qubits and interconnect buses). In contrast, a physical microarchitecture details the physical connectivity of physical qubits. For example, the physical microarchitecture of a QPU may comprise a uniform rectangular grid of many physical qubits with nearest-neighbour connectivity for the implementation of surface codes.

Quantum Architecture and Its Design

An ISA, logical microarchitecture, and physical microarchitecture together constitute a quantum architecture. Different microarchitectures can implement the same ISA. If the computation that needs to be run is already known, the microarchitecture can be designed to improve the execution time, physical resources (quantum and classical), and their trade-offs. Design choices include, for example, the number, type, and logical design of modules, the logical connectivity between these modules, which QEC scheme is employed, and what code distances are used in each module.

TopQAD’s Compiler optimizes the execution of the quantum algorithm at the level of the ISA, while its Assembler determines and optimizes a complete quantum microarchitecture by taking target hardware specifications into consideration with the help of TopQAD’s Noise Profiler.

In classical computing, an assembler is a type of very-low-level compiler that converts assembly language code into binary machine instructions. In contrast, a quantum assembler requires information about the non-idealities of the QPU, and therefore the software compilation hierarchy is not as detached from the hardware microarchitecture as it is in the case of classical computers. Therefore, TopQAD’s Assembler receives information from both the Compiler and the Noise Profiler to generate machine-level instructions for the QPU controllers and co-processing decoders. Different details about the resulting optimized microarchitecture are determined by the different tools in TopQAD. For example, the microarchitecture of core processors are completely determined after running the Compiler; however, detailed layouts of other modules are determined by the Assembler.

In this aspect, TopQAD can thus be viewed as an operating system (OS) for future quantum computers. In order to build these computers, it is important to envision their quantum architectures and required constituent redundancies in quantum and classical processing resources. Today, well before the use of TopQAD as an OS, it functions as an automated design tool for QPU architectures. TopQAD provides the means for designing and optimizing quantum architectures. This enables TopQAD’s QRE service to provide reliable and detailed resource estimates, which are crucial for the following reasons:

• Given the complexity and cost of building quantum computers, an efficient microarchitecture can make or break the opportunity to realize a quantum advantage; and
• Designing the microarchitecture enables careful tracking of the runtime of quantum applications, including determining concrete estimates of the resources that will be needed.

Quantum Architecture Example

Described below is an ISA using the Pauli product rotations gate set and example logical and physical microarchitectures that implement this ISA using the rotated surface code. This quantum architecture is currently supported by TopQAD and additional ISAs and microarchitectures will be supported in the future. If you work with a quantum computing technology that has specific quantum architecture requirements, reach out to 1QBit via e-mail .

Pauli Product Rotations ISA

The Pauli product rotations ISA provides a robust framework for FTQC. This ISA uses a gate set based on Pauli product rotations, which are executed through Pauli measurements and the consumption of $T$ magic states, as required for achieving universality in quantum computing (for more information, refer to the section on the Compiler. Fault-tolerant operations are performed using long-range teleportations, which are implemented via lattice surgery involving a quantum bus in the logical microarchitecture. Lattice surgery enables the manipulation of logical qubits by merging and splitting encoded patches using auxiliary logical qubits to ensure the integrity of quantum information during operations. This technique allows scalable architectures, such as those generated in TopQAD, to be designed such that error correction is controlled with optimal resource usage.

Microarchitecture Implementing the Pauli Product Rotations ISA
As an example, we consider a microarchitecture that implements the Pauli product rotations ISA using the rotated surface code, a quantum error-correcting code (QECC) scheme supported by TopQAD.

Modules

Here, we describe the modules of the example microarchitecture. Note that these modules consider high-fidelity magic states, which are required to perform FTQC.

• Core processor: This module includes a memory zone, where the quantum operations of the input quantum circuit are executed, and a layout-specific auto-correction zone [3, 4] that stores magic states to be consumed within the memory zone. In the auto-correction zone there can be one or more auto-correction units. Multiple auto-correction units can be used to inject magic states into the memory zone in parallel. The layout of the memory zone can impact how efficiently logical operations can be performed. Increasing the size of the auto-correction zone increases the capacity to hold magic states. This increases the ability to parallelize operations in the memory zone and handle fluctuations in magic state production and consumption more robustly.

• Magic state factory (MSF):
  Magic states are required by non-Clifford Pauli rotation gates. This module produces high-fidelity magic states through a sequence of distillation steps. There are several units within the module. Low-fidelity magic states are initially created in preparation units and then passed through multiple distillation levels to reach the required fidelity. At each level, lower-fidelity magic states are consumed by distillation units to produce a smaller number of higher-fidelity magic states. Once successfully distilled, the higher-fidelity magic states are sent upstream in the microarchitecture.

  The final, highest-fidelity magic states, prepared through multiple distillation levels, are passed to and stored in the auto-correction zone so they can be accessed for operations in the core processor. Optimizing the microarchitecture of the magic state factory is critical for the efficient production of a reliable supply of high-fidelity magic states.

Rotated Surface Code and Lattice Surgery

The details of the logical microarchitecture beyond the module level are deeply connected to the QECC scheme used to implement the ISA.

The rotated surface code can be implemented by a 2D lattice of qubits, typically visualized as a checkerboard of the $X$ and $Z$ stabilizers of the code. A microarchitecture using the rotated surface code can be partitioned into a number of tiles; see Ref. [3] for details. Single or multiple tiles can be grouped to form surface code patches, which may host one or more logical qubits. The logical operations (Pauli-$X$ or Pauli-$Z$) of the patches can be accessed through the edges of the patch. The resilience of a QECC to errors is described by its code distance. A single tile of the rotated surface code with distance $d$ has $2d^{2}-1$ physical qubits.

In this example microarchitecture, the following patch types exist:

• bus patches are dedicated for lattice surgery, the long-range measurement procedure indicated by the ISA. Together, the bus patches comprise the quantum bus. At every logical cycle, a subset of bus tiles is temporarily used to generate entanglement and connect distant logical qubits. These bus patches must connect to the data patches by the edges (i.e., $X$ or $Z$) required by their Pauli operators. Multiple lattice surgeries can be performed in the quantum bus in parallel, to perform multiple operations simultaneously, as long as their bus patches do not overlap. In this microarchitecture example, bus patches are one-tile patches.
• computational qubit patches store the data required for computation. These patches are associated with the qubits requested by the Pauli operators of the gates in the circuit to be scheduled. In this example, computational qubit patches are two-qubit, two-tile patches. Although computational qubits can generally be one-tile patches, two-tile patches facilitate the scheduling of gates that request Pauli-$Y$ operators. $Y$ operators can be performed only by entangling the $X$ and $Z$ operators of a qubit simultaneously along one of the edges in the patch associated with the qubit.
• magic state storage patches temporarily store a logical qubit in a magic state. Magic state storage patches are particularly useful for creating buffers between modules on the microarchitecture to improve the reliability of the magic state supply chain.
• magic state preparation patches are the patches that constitute the magic state preparation units introduced in the description of MSFs.
• correction qubit patches are dedicated to initializing qubits in the $\ket{0}$ state, which are required for performing Clifford operations, such as the Pauli corrections required when implementing $P_{\pi/8}$ rotation gates; see Refs. [4, 5]. These are two-tile patches and $Y$ operators are performed using them.
• output patches are where the quantum state generated by a given distillation unit is held for access by successive zones.
• distillation unit (DU) data qubit patches are single-tile patches used during magic state distillation to detect errors via stabilizer measurements. In protocols like 15-to-1 distillation, they are initialized in known eigenstates, participate in encoding and decoding, and are measured after the $T$ gates to check for errors. An outcome of $-1$ indicates a fault, and the magic state is discarded.
• code growth patches are to expand magic states to a higher code distance. This is required when a given unit or module outputs a magic state with a code distance lower than that required in the following unit or module.

Logical Microarchitecture Layout

The logical microarchitecture is visualized by a logical microarchitecture layout, which shows how modules, units, and patches of the logical microarchitecture are arranged and connected.

To learn more about how operations are scheduled on the microarchitecture, please see Compiler.