TopQAD Documentation

Quantum Resource Estimation (QRE)

This page uses the terminology and concepts discussed in the Quantum Architecture Basics section.

Introduction

**Figure 7.** Flow diagram of TopQAD’s QRE service, which employs all of TopQAD’s tools in a pipeline (illustrated within the dashed blue line) to provide quantum resource estimates. It invokes the **Assembler** to determine and optimize the logical and physical microarchitecture by considering both the compiled quantum algorithm’s output from the Compiler and the target hardware specifications as processed by the Noise Profiler into logical error rates. Note that, while the microarchitecture of core processors are completely determined after running the Compiler, detailed layouts of other modules are determined by the Assembler.

The QRE service helps you design and evaluate fault-tolerant quantum computers and their applications, prior to physical devices being built. The service uses a software pipeline that invokes TopQAD’s Compiler, Noise Profiler, and Assembler tools. These tools form the basis of a real quantum computer’s software compilation stack, turning a high-level quantum algorithm into machine-level instructions for the quantum computer. They can be incorporated as built-in components of a quantum OS that would run applications on the quantum hardware stack, while also deploying diagnostics, maintenance, and calibration processes. It is this level of operational detail that enables the QRE service to perform comprehensive quantum architecture design and resource estimation.

The QRE service designs a fault-tolerant quantum microarchitecture (see Assembler) for an input quantum algorithm, error budget, and a set of hardware specifications. The hardware specifications are used to determine (see Noise Profiler) the performance of FTQC protocols¹ that are needed for universal FTQC. The microarchitecture is designed to minimize the runtime of the compiled quantum algorithm (see Compiler), as well as the physical qubit count, while staying within the error budget. After this optimization, the service generates a report on the designed microarchitecture, including concrete resource estimates and other operational details. Thus, the QRE service allows you to run experiments to explore design and resource trade-offs, helping to answer questions such as the following:

To what extent does a given system for quantum computation have to scale to achieve practical utility?
How many physical qubits are required to run an algorithm, given hardware specifications (e.g., qubit and gate fidelities) such as those currently available?
Where should development efforts be focused to overcome bottlenecks (e.g., in decoders or specific hardware components)?
How are physical resources allocated across different modules, such as the core processor and magic state factory?

Portal Specifications

QRE Portal Access Specifications

Inputs

	Parameter	Description
General	Error budget	The maximum accumulated error tolerated across the computation.
	Circuit file	Circuits written in an intermediate representation (IR) will be accepted. Currently, the OpenQASM 2.0 format is supported. Soon, richer IR languages will also be supported. Alternatively, users can choose to run a circuit from the pre-loaded circuit library.
	Repeat input circuit	Sometimes users may wish to repeat an input circuit. An example of this is in the case of Trotterization, where each Trotter step repeats the same circuit. If this option is selected, the Compiler is run once for the input circuit, but subsequent steps in the QRE service will utilize the repeated circuit. If this option is not selected, the input circuit will be the circuit used in the resource estimation as is.
	Number of repetitions	The number of times to repeat the circuit, if “Repeat input circuit” is selected.

Advanced configurations

	Parameter	Description
Code	Specifier	The QECC to use. Currently, the “Rotated surface code” is supported.
Code	Protocol	TopQAD currently uses the memory protocol in the QRE service.
Physical qubit and gate characterization	Qubit measurement time	The time taken to measure a qubit.
	Qubit preparation time	The time taken to prepare a qubit in a zero or one state at the start of a protocol.
	Qubit reset time	The time taken to reset a qubit to the zero state mid-protocol.
	Single-qubit gate time	The time taken to implement single-qubit gates (e.g., the Hadamard gate).
	Two-qubit gate time	The time taken to implement two-qubit gates (e.g., the controlled-NOT, or CNOT, gate).
	T1 relaxation time	The relaxation time for a qubit.
	T2 dephasing time	The dephasing time for a qubit. Currently, TopQAD requires this value to be equal to the T1 relaxation time.
	Measurement fidelity	The fidelity of measuring a physical qubit, that is, the average probability of an output of 0 when measuring the zero state and an output of 1 when measuring the one state.
	Preparation fidelity	The fidelity of preparing a qubit at the start of the protocol, that is, the average probability of preparing the zero state when trying to prepare the zero state, and preparing the one state when trying to prepare the one state.
	Reset fidelity	The fidelity of resetting a qubit mid-protocol, that is, the average probability of correctly resetting to the zero state regardless of the outcome of the preceding measurement.
	Single-qubit gate fidelity	The fidelity of implementing single-qubit gates (e.g., the Hadamard gate).
	Two-qubit gate fidelity	The fidelity of implementing two-qubit gates (e.g., the CNOT gate).

Outputs

	Parameter	Description
Summary	Expected runtime	The expected time needed to perform a quantum computation.
Summary	Number of physical qubits	The estimated number of physical qubits required for the computation.
Microarchitecture visualizer	Microarchitecture visualizer	A visualization of the generated logical microarchitecture layout. The layout follows the conventions detailed in the legend of Fig. 1 in the Quantum Architecture Example section. However, the visualizer has one element that differs from this legend; there are boxes with dashed-line edges, which indicate areas of the logical microarchitecture layout that are not currently generated by the visualizer in tile-level detail.
Compiled circuit	Compiled circuit	A detailed list of the lattice surgeries performed in the memory zone of the core processor, including which qubits are required for each operation within the memory zone, which magic state storage patch is used, and at which logical cycle time step the surgeries are performed.
Circuit details	ISA gate set	The ISA gate set used to represent operations in the circuit as required for the output architecture. The Pauli product rotations gate set is currently supported.
	Number of computational qubits required	The number of logical qubits used in the computation.
	Number of operations	The total number of operations in the synthesized circuit, as well as breakdowns by the number of Clifford rotations (e.g., $P_{\pi/4}$ rotations), non-Clifford rotations (e.g., $P_{\pi/8}$ rotations), and logical measurements.
Accumulated error bounds	Total	An upper bound on the computational error accumulated from the following sources: circuit synthesis, core processor, and MSF.
	Synthesis error	Synthesis error
	Core processor error	Core processor error
	Magic state factory error	Magic state factory error
Logical resources	Tile count	Output that includes the tile count by type (e.g., bus, computational qubit, and magic state storage) and area (e.g., memory zone, auto-correction zone, and MSF).
Physical resources [core processor]	Code distance	The code distance for encoding logical qubits in the core processor.
	Number of physical qubits per logical qubit	The number of physical qubits used to encode each logical qubit in the core processor.
	Total number of physical qubits	The total number of physical qubits in the core processor.
Physical resources [magic state factory]	Code distance per distillation level	The code distance for encoding logical qubits at each distillation level. When multiple distillation levels are present, the code distance for each level is shown separated by a comma in ascending order by level.
	Number of physical qubits per logical qubit per distillation level	The number of physical qubits used to encode a logical qubit at each distillation level. When multiple distillation levels are present, the value for each level is shown separated by a comma in ascending order by level.
	Total number of physical qubits per distillation level	The total number of physical qubits at each distillation level. When multiple distillation levels are present, the value for each level is shown separated by a comma in ascending order by level.
	Total number of physical qubits	The total number of physical qubits in the magic state factory.
Magic state factory	Number of distillation levels	The number of distillation levels.
	Distillation protocol per level	The distillation protocol used by the units at each level.
	Number of distillation units	The number of distillation units at each level.
	Distillation runtime	The time required for one distillation cycle.
	Acceptance probability	The probability of a distillation cycle successfully distilling higher-fidelity magic states.
	Logical magic state error rate	The error rate attained for the designed magic state factory.
Noise profiling [general]	Physical qubits formula	The formula used to determine the number of physical qubits used to encode one logical qubit.
	Stabilization time	The time taken to perform one cycle of stabilizer measurements (i.e., parity checks on QEC codes).
	Functional form	The fitting function for the logical error rate as a function of distance.
	Fitting parameters	For the memory protocol, the logical error rate as a function of the distance. The logical error rate is fit, and the fitting parameters are returned. The fitting parameter $b$ determines the rate at which the logical error rate decreases with distance, while the parameter $a$ determines the rate at low distances.
Noise profiling [core processor]	Logical qubit error rate	The projected error rate for operations performed using logical qubits within the core processor. This rate is derived from a regression model that predicts logical performance based on the required code distance, as determined by the Noise Profiler. It reflects the expected reliability of logical qubit operations given the underlying physical noise characteristics and error correction parameters.
	Logical cycle time	The time taken to perform one logical operation using logical qubits at the chosen code distance.
	Decoder bandwidth	The rate, in bytes per second, at which the decoder must process syndrome data to determine corrections. A decoder operating at a lower rate will create a backlog of syndrome data, leading to a loss of fault tolerance in the system.
Noise profiling [magic state factory]	Logical magic state preparation error rate	The error rate of the magic states prepared from physical qubits.
	Clifford error rate per distillation level	The error rate of the Clifford operation that is performed in a given distillation level. When multiple distillation levels are present, the value for each level is shown separated by a comma in ascending order by level.
	Logical cycle time	The time taken to perform one logical operation using logical qubits at the chosen code distance at each distillation level.
	Decoder bandwidth	The rate, in bytes per second, at which the decoder should process syndrome data to determine corrections. A decoder operating at a lower rate will create a backlog of syndrome data, leading to a loss of fault tolerance in the system.
Scheduling [number of active logical cycles]	Expected	The number of active logical cycles² that TopQAD estimates are required to execute the circuit compiled on the generated core processor microarchitecture.
	Lower bound (most-parallelized execution)	The lower bound of the number of active logical cycles required for the scheduling, based on the dependency relationship between operations in the circuit.
	Upper bound (serial execution)	The upper bound of the number of active logical cycles required for the scheduling, based on the execution of operations in serial.
Scheduling [lattice surgery size histogram]	Lattice surgery size histogram	A plot showing how frequently lattice surgeries of a given bus size are required in the compiled circuit. Size is measured by the number of bus patches and includes patches in both the memory and auto-correction zones.

SDK Specifications

QRE SDK Access Specifications

The release of an SDK is upcoming; stay tuned.

Currently, the performance of quantum memory is used to approximate the performance of other protocols, though a complete set of protocols (e.g., quantum memory, magic state preparation, magic state distillation, code growth, and multi-qubit lattice surgery) will soon be made available for increased accuracy. ↩
I.e., the number of logical cycles when the core processor is executing logical gates (active). ↩