Compiler
This page uses the terminology and concepts discussed in the Quantum Architecture Basics section.
Introduction
Figure 5. Flow diagram of TopQAD’s Compiler service, which runs the Compiler tool to optimize the execution of the quantum algorithm at the level of the ISA, scheduling operations on a determined logical microarchitecture for a specific module, the core processor.
The Compiler service allows you to study, test, and evaluate algorithms independently of the hardware noise model while considering the core processor’s microarchitecture layout. You can use the Compiler to answer questions such as the following:
- What logical resources (e.g., count and logical qubits) are required in the core processor to run a quantum algorithm within a desired target error rate?
- What are the expected bus sizes in the lattice surgeries of the compiled program?
- Which patches in the core processor microarchitecture are used most frequently and should therefore be assigned to higher-fidelity qubits?
- Are there any patches causing bottlenecks for the lattice surgeries? If so, could a different core processor microarchitecture mitigate this issue?
Portal Specifications
Compiler Portal Access Specifications
Inputs
| Parameter | Description | |
|---|---|---|
| General | Error budget | The maximum accumulated error tolerated when converting the gates in the input circuit to the required ISA (currently a Pauli product rotations ISA), input in decimal format. |
| Circuit file | Circuits written in an intermediate representation (IR) will be accepted. Currently, the OpenQASM 2.0 format is supported. Soon, richer IR languages will also be supported. Alternatively, users can choose to run a circuit from the pre-loaded circuit library. | |
| Remove Clifford gates | A toggle for whether all Clifford gates should be removed from the circuit. If selected, this option allows the final circuit to be much more compact, containing only rotation gates. This may reduce the number of active logical cycles and overall quantum runtime. Otherwise, Clifford gates are kept for sparser Pauli operators, leading to a greater parallelization potential and shorter-range lattice surgeries. | |
| Insights only | An option to run the compiler faster by skipping the generation of the compiled circuit file. All other outputs listed below will be displayed. |
Outputs
| Parameter | Description | |
|---|---|---|
| General | Compiled circuit | A detailed list of the lattice surgeries performed in the memory zone of the core processor, including which qubits are required for each operation within the memory zone, which magic state storage patch is used, and at which logical cycle time step the surgeries are performed. |
| Elapsed time | The time taken to run the Compiler. | |
| Synthesis error | The error accumulated by the circuit synthesis process during compilation. | |
| Circuit details | ISA gate set | The ISA gate set used to represent operations in the circuit as required for the output architecture. The Pauli product rotations gate set is currently supported. |
| Number of computational qubits required | The number of logical qubits used in the computation. | |
| Number of operations | The total number of operations in the synthesized circuit, as well as breakdowns by the number of Clifford rotations (e.g., rotations), non-Clifford rotations (e.g., rotations), and logical measurements. | |
| Core processor specifications | Number of tiles | The tile count in the core processor by type (e.g., bus, computational qubit, and magic state storage) and region (e.g., memory zone or auto-correction zone), as well as the number of auto-correction units. |
| Number of auto-correction units | The number of auto correction units in the auto-correction zone. | |
| Scheduling [number of active logical cycles] | Expected | The number of active logical cycles1 that TopQAD estimates are required to execute the circuit compiled on the generated core processor microarchitecture. |
| Lower bound (most-parallelized execution) | The lower bound of the number of active logical cycles required for the scheduling, based on the dependency relationship between operations in the circuit. | |
| Upper bound (serial execution) | The upper bound of the number of active logical cycles required for the scheduling, based on the execution of operations in serial. | |
| Scheduling [lattice surgery size histogram] | Lattice surgery size histogram | A plot showing how frequently lattice surgeries of a given bus size are required in the compiled circuit. Size is measured by the number of bus patches and includes patches in both the memory and auto-correction zones. |
SDK Specifications
Compiler Software Development Kit (SDK) Access Specifications
The release of an SDK is upcoming; stay tuned.
Footnotes
-
I.e., the number of logical cycles when the core processor is executing logical gates (active). ↩