TopQAD1Qbit

Compiler

This page uses the terminology and concepts discussed in the Quantum Architecture Basics section.

Introduction

Figure 5. Flow diagram of TopQAD’s Compiler service, which runs the Compiler tool to optimize the execution of the quantum algorithm at the level of the ISA, scheduling operations on a determined logical microarchitecture for a specific module, the core processor.

The Compiler service allows you to study, test, and evaluate of algorithms independently of the hardware noise model while considering the core processor’s microarchitecture layout. It converts gates from an intermediate representation (IR) format to an ISA, as described in TopQAD's Tools >> Compiler. For example, in order to convert to the Pauli product rotations ISA, TopQAD approximates single qubit rotations using the gridsynth algorithm [6]. The process of approximating gates using a discrete gate set will incur synthesis error; the service will ensure that this error falls within an allowed error budget as described in TopQAD's Tools >> Compiler section.

You can use the Compiler to answer questions such as the following:

  • What logical resources (e.g., TT count and logical qubits) are required in the core processor to run a quantum algorithm within a desired target error rate?
  • What are the expected bus sizes in the lattice surgeries of the compiled program?
  • Which patches in the core processor microarchitecture are used most frequently and should therefore be assigned to higher-fidelity qubits?
  • Are there any patches causing bottlenecks for the lattice surgeries? If so, could a different core processor microarchitecture mitigate this issue?

Portal Specifications

Compiler Portal Access Specifications

Inputs

ParameterDescription
GeneralError budgetThe maximum accumulated error tolerated when converting the gates in the input circuit to the required ISA (currently a Pauli product rotations ISA), input in decimal format.
Circuit fileA quantum circuit file. The Compiler service supports a subset of the language features of OpenQASM 2.0 format. Currently, users can choose circuits from a select library of example circuits. The option to upload your own circuits will be available shortly, and further details on the supported OpenQASM 2.0 format will be provided. Support for richer quantum languages will be added soon.
Remove Clifford gatesA toggle for whether all Clifford gates should be removed from the circuit. If selected, this option allows the final circuit to be much more compact, containing only Pπ/8P_{\pi/8} rotation gates. This may reduce the number of active logical cycles and overall quantum runtime. Otherwise, Clifford gates are kept for sparser Pauli operators, leading to a greater parallelization potential and shorter-range lattice surgeries.
Insights onlyIf selected, the QRE service will skip the generation of the detailed compiled circuit when generating the QRE report. This allows for faster report generation and reduced resource usage.

Outputs

ParameterDescription
GeneralCompiled circuit

A detailed list of the lattice surgeries performed in the memory zone of the core processor, including which patches are required for each lattice surgery and the order in which these surgeries are performed. This is only provided if the Insights only toggle is disabled. It is a JSON file in the format <time step>: [<operation ID>, [<patch connections used by the lattice surgery>]]. An example is shown below:

[
    {"0": [
        [0, [[["m0", "Z"], 1], [1, 2], [2, 6], [6, ["q1", "Z"]]]], 
        [2, [[["m1", "Z"], 4], [4, 7], [7, 5], [5, ["q0", "Z"]]]]]
    ]},
    {"1": [
        [1, [[["m0", "Z"], 1], [1, 2], [2, 6], [6, ["q2", "Z"]]]], 
        [3, [[["m1", "Z"], 4], [4, 7], [7, ["q3", "Z"]]]]]
    ]}
]
Elapsed timeThe time taken to run the Compiler.
Synthesis errorThe error accumulated by the circuit synthesis process during compilation.
Circuit detailsISA gate setThe ISA gate set used to represent operations in the circuit as required for the output architecture. The Pauli rotations gate set is currently supported.
Number of computational qubits requiredThe number of logical qubits used in the computation.
Number of operationsThe total number of operations in the synthesized circuit, as well as breakdowns by the number of Clifford rotations (e.g., Pπ/4P_{\pi/4} rotations), non-Clifford rotations (e.g., Pπ/8P_{\pi/8} rotations), and logical measurements.
Core processor specificationsNumber of tilesThe tile count in the core processor by type (e.g., bus, computational qubit, and magic state storage) and region (e.g., memory zone or correction zone), as well as the number of correction units.
Number of correction unitsThe number of correction units in the correction zone.
Scheduling
[number of active logical cycles]		ExpectedThe number of active logical cycles1 that TopQAD estimates are required to execute the circuit compiled on the generated core processor microarchitecture.
Lower bound (most-parallelized execution)The lower bound of the number of active logical cycles required for the scheduling, based on the dependency relationship between operations in the circuit.
Upper bound (serial execution)The upper bound of the number of active logical cycles required for the scheduling, based on the execution of operations in serial.
Scheduling
[lattice surgery size histogram]		Lattice surgery size histogramA plot showing how frequently lattice surgeries of a given bus size are required in the compiled circuit. Size is measured by the number of bus patches and includes patches in both the memory and correction zones.

Footnotes

  1. I.e., the number of logical cycles when the core processor is executing logical gates (active). ↩